Some conventional systems include one or more processor chips mounted to a printed circuit board (PCB) and communicating with memory modules. Thus, in one example, a processor chip is mounted on a PCB and communicates with the memory modules by traces in the PCB. During normal operation, the processor issues read requests and write requests to the memory.
In high bit rate operations, capturing bits may become a challenge because the time window in which to capture a given bit becomes short. Furthermore, various phenomena, such as electromagnetic reflections in the metal traces, may negatively affect the time window in which to capture a given bit. This is especially true for PCBs that are set up with a daisy chain connection from the processor to the memory modules. In the daisy chain architecture, each of the memory modules are connected to a common bus, and electromagnetic reflections may affect the capture of bits at memory modules that are closer to the processor. Thus, severity of electromagnetic reflection phenomena as seen at the nearer memory modules may set a limit as to a maximum bit rate between the processor in the memory modules.
Conventional Tee topology might be used in some solutions, though a conventional Tee topology may be expected to result in diminished performance if only one memory module is used on the PCB. Thus, conventional Tee topology might prevent use of a given board design in single-module applications.
Accordingly, there is a need in the art for systems and methods that allow for increasing bit rates and reduced harmful phenomena, such as electromagnetic reflection.